Announcing new training modules around DVCon India 2016

Being a world-leader in VLSI Design & Verification training, VerifLabs (A training arm of CVC) is proud to announce new training modules. While there are many other training institutes, NONE of them have ever presented high-quality paper at leading edge industry conferences such as DVCon with contributions from trainees – this is what trainees at VerifLabs/CVC get exposed to – learn advanced DV technologies like a professional and showcase it to the world’s best engineers at premier events like DVCon.

At DVCon India 2015 our team presented 2 papers: (From archives of DVCon India 2015):

Intelligent Coverage Driven, Modern Verification for VHDL Based Designs in Native VHDL with OSVVM, Anupam Maurya, Vijay Mukund Srivastav and Prabhat Kumar, CVC Download the PDF here.

Increase Productivity with Reflection API in Design Verification Shivayogi Kerudi, Vijay Mukund Srivastav, Vani S, CVC and Dr. Brad Quinton, Invionics. Download the PDF here.

We also contributed to the promotions committee through our CEO, Ajeetha’s popular DVCon Countdown.

Now at DVCon India 2016, our team is proud to have been selected to present 2 papers:

Verify thy Verifier via SVUnit – https://dvcon-india.org/content/event-details?id=205-12

You can download the abstract from here.

Hidden gems of UVM Base Class Library – debug techniques for UVM users,
https://dvcon-india.org/content/event-details?id=205-15

So next time when someone asks to you choose a training institute for VLSI, ask them if they need just a training or a great career with passion! If latter, contact VerifLabs via +91-9620209223

With the above 2 papers being presented at upcoming DVCon India 2016, it is no surprise that we are announcing new training modules with hands-on labs on the same topics. Below are some of the latest modules being rolled-out:

  • Unit testing for “checkers” (Extending our “Verify thy verifier” paper)
  • PSS – the next BIG thing in DV (and a MUST have in your resume soon) – see: Portable Stimulus training – coming soon at CVC/VerifLabs
  • Art of debugging with UVM (Extending our “UVM debug” paper, using our home-grown UVM Vault technology, see below for a screenshot)

VW_UVM_Vault

 

So do visit us at DVCon India 2016 and learn how we could help you with the latest in DV space.

 

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