SV Design Training(VL-SV Design)

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SystemVerilog is a unified hardware design, specification, and verification language. SystemVerilog enables the use of a unified language for abstract and detailed specification of the Digital system design. It offers a vendor-independent API to access proprietary waveform file formats, and a direct programming interface (DPI) to access proprietary functionality. It also offers methods that allow designers to continue to use present design languages when necessary to leverage existing designs and intellectual property.

This training session covers RTL modeling and higher level modeling Using SystemVerilog and explains the Key benefits of SystemVerilog over Verilog.

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Good knowledge in HDL coding using Verilog-2001(must) and VHDL (preferable).

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  • Introduction
    • Objectives of this course
    • Structure of the course
    • Language evolution
    • Major parts of SV
  • Data Types
    • Enhanced, New data types
    • Type checking, casting
    • Structures,unions
  • Modeling combinatorial logic
    • Continuous Assignment
    • always_comb
    • case/if unique/priority
  • Modeling sequential logic
    • always_ff
    • always_latch
    • Modeling Clock gating
  • Enhanced constructs & New Constructs
    • Operators
    • Loops
    • Event
    • Labels, named blocks
  • Interface
    • As wire bundle
    • Real life usage
    • Modport
    • Interface methods
    • Success Story
    • Interface Synthesis
    • Compareandcontrasttostruct
    • More on interface
  • Arrays
    • V2K arrays – recap
    • Arrays in SV:
      • Packed
      • Unpacked
      • MDA
    • Accessing array elements
    • Querying Methods
    • Dynamic arrays
    • Associative arrays
    • Queues
    • Array methods
  • Package
  • Port connection rules


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This training session is intended for students, fresh graduates and hardware/software engineers who wish to learn about System Verilog.


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Full Day


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