Verification using SystemVerilog(VL-VSV)

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VerifLabs – a venture from CVC Pvt.Ltd.

What is SystemVerilog? 
SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog  for verification, design and synthesis. Enhancements range from simple enhancements to existing constructs, addition of new language constructs to the inclusion of a complete Object-Oriented paradigm features. There are also considerable improvements in the usability of Verilog for RTL desigin.

Overview:
CVC’s Verification Using SystemVerilog course gives you an in-depth introduction to the main enhancements that SystemVerilog offers for testbench development, discussing the benefits and issues with the new features. It also demonstrates how verification is more efficiently and effectively done using SystemVerilog constructs. The course explores in depth verification enhancements such as object-oriented design, constraint random generation, and functional coverage.