Verilog Training(VL-Verilog)

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IEEE 1364-2001Verilog – Training agenda

Table of Contents

Introduction

  • Introduction to top down digital design flow
  • Levels of abstraction –Structural, RTL, Behavioral
  • Introduction to Verilog HDL
  • Modeling at various abstraction levels

Verilog Basics

  • Anatomy of a Verilog Model
  • Data types
  • Logic Values
  • Identifiers
  • Numbers
  • Parameters
  • Procedural Blocks: Initial and Always
  • Continuous Assignments
  • Operators
  • Conditional Statements
  • Loop Statements

Behavioral Verilog

    • Procedural Constructs
    • Timing Control
    • Block Statements

-begin – end, fork – join

    • Procedural Continuous Assignments

-assign-deassign, force– release

Modeling Techniques

  • Combinatorial Logic
  • Sequential Logic
  • Gate Level Modeling
  • Switch Level Modeling

Miscellaneous

  • Compiler Directives
  • System Task and Functions
  • Array of instances
  • File IO
  • Memory modeling, array access

Synthesis Perspective

  • Synthesis flow in brief
  • Guidelines for Combinatorial block
  • Guidelines for Sequential block
  • Blocking & Non-blocking assignments
  • FF, latch inference
  • FSM Modeling

Verification Perspective

  • Verification Flow
  • Introduction to Testbench
  • Writing Test Bench
  • Sample Test Bench

Gate Level Modeling

  • Verilog Primitives
  • User Defined Primitives
  • Modeling Delays

Timing specification capture

  • Specify Block
  • Setup and Hold Time

Verilog PLI

  • Introduction to PLI
  • PLI Capabilities
  • Steps to Integrate PLI

Verilog 2001 Enhancements

Subroutines in Verilog

  • Task
  • Function
  • Subroutine types – Static and Automatic

Advanced Verilog

  • Compiler Diectives:`define,`undef,`resetall,`ifdef,`ifndef
  • Parameter
  • Generate
  • Timescale
  • Display Tasks-$display $monitor
  • Value Change Dump
  • Formattime, Timeformat, Printtimescale
  • Understanding Blocking and Non-blocking Assignments

VERILOG LABS

Lab1:Operators

Lab2: Data flow Modeling

Lab3:Behavioral Modeling

Lab4: Structural Modeling

Lab5: File IO

Lab6: Memory Modeling

Lab7: FSM

Lab8: UDP

Lab9: PLI

Lab10: case constructs

Lab 11:Tasks and Functions

Lab 12:Static vs Auto Functions & Tasks

ADVANCED VERILOG LABS

Lab1:Using define,ifdef,ifndef.

Lab2:Using defparam, Instantiation.

Lab3:  Using generate.

Lab 4:  Using Formattime, Timeformat, Printtimescale.

Lab 5:  Using Specify

Lab 6:  Using force and release

Lab 7:  Using Dump

Lab 8:  Using Protect