VerifLabs – a venture from CVC Pvt.Ltd.
What is UVM?
Universal Verification Methodology (UVM) is the industry standard Verification methodology for Verification usingSystemVerilog (SV). UVM provides a mean of doing verification in a well defined and structured way. It is a culmination of well known ideas, thoughts and best practices. It is also supported by a standard set of base classes to help building structured verification environment faster. More details about the standard can be found at: http://www.go2uvm.org
What’s a Do-it Right course?
Do-it Right is a series of methodology trainings from CVC for those who are familiar with the basics and want to do the verification the “right” way. For instance, SystemVerilog offers a
wide variety of features that can be used in many contexts. UVM helps to focus on end goal of achieving structured, reusable