Title: Verification using SystemVerilog
VerifLabs Team delivered work shop on VLSI Verification Topic at Thakur Institute of Career Advancement Like : Interface ,SystemVerilog, SVA .
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Event Date:from 11 to 15 Jan 2016.
Resource Person(s): Arun P.C, Sai Pranesh, VerifLabs – a venture from CVC Bangalore